Drawing Validation -- Automated Quality Assurance

[forumadmin]

The June 2012 release of DraftLogic Electrical includes a much-enhanced drawing validation tool. It runs automatically on drawing load. You can also trigger it as you desire with the Drawing Discovery > Check Blocks & Polys tool palette tool. We build this tool since most of our support calls end up being one of these issues. By having all drawings checked on load, we hope to make your design work easier by reallocating some drafting troubleshooting time back to design or client interaction time.

See this blog entry for some more general information about the drawing validation tool:
http://www.draftlogic.com/blog/2012/06/automatic-drawing-validation/

The drawing validation tool focuses on testing the four core requirements of the Drawing Discovery phase of work: room boundaries, room IDs, floor boundaries, and floor match blocks. Almost every conceivable issue with these elements is tested for. In addition, there are some basic tests run on all closed polylines used by DraftLogic Electrical & on all DraftLogic Electrical blocks--tests like ensuring that polylines are closed, have no concurrent vertices, and that there are no duplicate polylines or blocks.

Issues that DraftLogic Electrical is absolutely sure can be resolved in only one way, are done so automatically. You are notified of these fixes but do not have to take any action--the work is done.

Issues where there is any doubt of the resolution are flagged with error (aka warning) arrows and listed for you in a summary dialog that includes both the auto-fixes and the error arrowed items.

If no issues are found on the auto execution of the drawing validation tool that occurs on drawing load, there won't be a dialog box shown, just some 'all clear' notifications showing up in the command history:

Validator Tool: No Room or Floor Issues Found
Validator Tool: No other block and polyline Issues found

Here is a list of the conditions checked, what the treatment of each is, and for those where you are needed to resolve them we detail your options. Note that many of these conditions will trigger others. So, for example, a floor boundary or room boundary overlap can also trigger floor match or room ID error arrows if any of these are included in the overlapping area. Take a good look at what is going on before selecting your course of action to fix things up.

Silent automatic fix (means no error arrows, the dialog details ‘list of what DraftLogic Electrical did’ only) for:
(1) Delete polylines that are zero or near zero length.

(2) Remove zero length segments from all closed and open polylines.

(3) Close polylines that are open and have coincident or very near start/end point.

(4) Delete extras of room/floor/DLdevice-related polyline and block complete duplicates. ‘Complete duplicate’ means layer, xdata, attributes, and geometry are all perfect matches. Xdata perfect match to mean all string xdata entries are no-case equal.
(a) Delete the room boundary, floor boundary, floor match, and room ID complete duplicates
(b) Delete DraftLogic Electrical device complete duplicates. The devices are the blocks on the zDL* and xDL*layers.

(5) Erase entities not allowed from certain layers (details in addendum below)

(6) Perform some indisputably needed fixes to closed polylines, for example a zero width jut.

*** Please note that issues 1, 2, and 3 from above are actually VERY common. Most tools that create polylines with automation, including DraftLogic Electrical`s Automated Room Creation & Automated Branch Circuit Wiring, will generate a number of these types of issues as a part of doing their work. Cleaning them up does not harm the end product of their results, just makes the drawing cleaner and makes the polylines in question easier to process!

Mark with error arrows and list in the drawing validation results dialog, user to review and if necessary, resolve the issue:
(7) Room and Floor (zDL_ROOM_BDRY, zDL_FLOOR_OUTLINE) entities:
(a) Each polyline on room boundary layer should be closed. [Non zero length removal already done earlier] If you are familiar with PEDIT, you can try to use it to close the polyline. Most reliable method to resolve is to delete the offending boundary and redraw it from scratch.
(b) Same as '(a)' for each polyline on floor boundary layer, with same resolution options.
(c) Each room should have one and only one room ID in it (exception: room boundaries that are service areas of a clone type suite panel). To resolve, verify that the insertion point of each room ID is in the proper room (aka space). The actual visible text of the room ID block are recommended to be in the space they apply to for your understandability but don't need to be...it is the insertion point that matters. If excess room ID blocks have been placed, delete them.

(8) Each room ID should be in one and only one room. Pretty well the only way a room ID will be in more than one room will be a room boundary overlap, so you need to fix that anyway.

(9) No overlaps between room boundaries or between floor boundaries, including self-intersection. Use the grip edits, aka vertices, on the boundary to move things around so the space you want enclosed is still covered, but there are not any overlaps. Worst case, delete the offending boundary and redraw it.

(10) Each room boundary must be in one and only one floor boundary. To have a room boundary be in more than one floor boundary, either the room boundary is spilling out of one floor boundary's area and into another or there is a floor boundary overlap. Same method to resolve as #7.

(11) Each floor should have one and only one floor match block in it. Even when the dwg has only one floor boundary in it, that floor boundary must have a floor match block in it. Errors of this type mean either extra floor match blocks in a floor or a floor boundary overlap wherein the extra space taken includes the floor match boundaries of both floors. For extra floor IDs, delete the excess--keeping the one that is in the same vertical position on the building as the other floor match blocks. For boundary issues, use the same method to resolve as #7.

(12) Each floor match block should be in one and only one floor boundary. For a floor match block to be in more than one floor, there must be a floor boundary overlap. Same method to resolve as #7.

(13) No overlaps between floor boundaries. Same method to resolve as #7.

(14) Ensure each floor boundary closed polyline has a numeric decimal floor ID in its xdata (positive & negative whole number and decimal values allowed) & that there are no duplicate values (compare exact values without rounding as there are cases where someone might want floor 1 for one floor boundary and 1.000001 for another floor boundary and this would be legitimate. The xdata is FLOOR_ID@DL_FLOOR. Use the Drawing Discovery > Edit Floor ID tool to both check floor IDs & change any errant ones. If you have areas that are separate on the DWG but that should be on same/similar floors, use close numbers like 1.00 and 1.00001.

(15) Plot area layer (zDL_PLOTAREA), and circuiting service area layer (zDL_SERVICEAREA) polylines should be closed. Use same resolution as for (5)(a).

(16) Identify possibly duplicate DraftLogic Electrical blocks and polylines. User should carefully review and remove any redundant blocks/polylines; also ensure that near duplicates that are 'valid' have everything reasonably done to them to differentiate between them.

Remember that one of the keys to success with DraftLogic Electrical, or any new software you are learning, is not to spin your wheels and get frustrated by spending too much time trying to resolve an issue on your own. So take your best shot to deal with any issues, but if a few minutes doesn't yield an acceptable resolution, pick up the phone and call us for support!

[forumadmin]

Build 3.0.0.588 (August 2012) and later include a segregation of Drawing Validator identified issues into 'critical' and 'noncritical' categories.

For now, we have changed the messaging on the Drawing Validator dialog to advise of you the critical issues and ask you to resolve them before the process you requested will run...but at this time it is an empty threat

We're going to run as such for some time to ensure that the identified issues truly are critical and are within your means to resolve (i.e. before you block any processes due to 'unresolved critical issues').

Also, the Drawing Validator as of this build has been enhanced to check/perform:
A. That all DraftLogic Electrical devices that should be within a room (aka space) boundary are within one.
B. Automatic removal of boundary single vertex offshoots, ie where a boundary goes out to a vertex and immediately returns to the vertex it just left from. The offshoots are removed and the polyline is closed, making the existing polyline usable rather than something that needs to be replaced.
C. Identification of repeated vertices in closed polylines-- user to delete and redraw.

[forumadmin]

Build 644 and later (644 was a mid October 2012 release) include a new Drawing Validation step to automatically clear 'undesired' entities from DraftLogic Electrical working layers.

Basically, any entity of a type that has not been specifically allowed will be deleted. This only affects specific DraftLogic Electrical non-electrical device layers that have been loaded into the database for such management.

For this first release of this new 'housecleaning' function, here's the layers that we have set up for entity type check and the allowed entity types:

zDL_WALL, zDL_WINDOW, zDL_DOOR allow LWPOLYLINE, ARC, LINE, TEXT, MTEXT, and INSERT (i.e. blocks)

zDLWRK* allow LWPOLYLINE, ARC, LINE (eight layers, all with zDLWRK prefix typically generated by Automated Room Creation to hold simplified representations of doors, walls, windows)

As with the other Drawing Validation automatic fixing/cleanup, you will be notified if any entities are deleted. No other layers other than the total eleven specified above are examined for allowed entity types.